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[Author] Takao ONOYE(65hit)

61-65hit(65hit)

  • Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol

    Yoshihiro OHTANI  Nobuyuki KAWAHARA  Hiroyuki NAKAOKA  Tomonobu TOMARU  Kazuhito MARUYAMA  Toru CHIBA  Takao ONOYE  Isao SHIRAKAWA  

     
    PAPER

      Vol:
    E85-B No:10
      Page(s):
    2032-2043

    A new error correction block based Hybrid ARQ protocol, in which PHY layer packets are composed of multiple error correction blocks, is devised together with a retransmission control scheme constructed on the basis of these error correction blocks. This protocol is designed dedicatedly for mobile AV stations to provide the high quality digital video transmission through a radio channel. To analyze the performance of this protocol, the frame loss rate vs. the uncorrectable error probability is simulated, in comparison with the ordinary packet based retransmission control. A wireless video transmission system using IEEE802.11b PHY is also described, which has been developed with the use of a Medium Access Control (MAC) LSI to perform the proposed protocol.

  • A Node-Grouping Based Spatial Spectrum Reuse Method for WLANs in Dense Residential Scenarios

    Jin LIU  Masahide HATANAKA  Takao ONOYE  

     
    PAPER-Mobile Information Network and Personal Communications

      Vol:
    E103-A No:7
      Page(s):
    917-927

    Lately, an increasing number of wireless local area network (WLAN) access points (APs) are deployed to serve an ever increasing number of mobile stations (STAs). Due to the limited frequency spectrum, more and more AP and STA nodes try to access the same channel. Spatial spectrum reuse is promoted by the IEEE 802.11ax task group through dynamic sensitivity control (DSC), which permits cochannel operation when the received signal power at the prospective transmitting node (PTN) is lower than an adjusted carrier sensing threshold (CST). Previously-proposed DSC approaches typically calculate the CST without node grouping by using a margin parameter that remains fixed during operation. Setting the margin has previously been done heuristically. Finding a suitable value has remained an open problem. Therefore, herein, we propose a DSC approach that employs a node grouping method for adaptive calculation of the CST at the PTN with a channel-aware and margin-free formula. Numerical simulations for dense residential WLAN scenario reveal total throughput and Jain's fairness index gains of 8.4% and 7.6%, respectively, vs. no DSC (as in WLANs deployed to present).

  • Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL

    Takao ONOYE  Gen FUJITA  Masamichi TAKATSU  Isao SHIRAKAWA  Nariyoshi YAMAI  

     
    PAPER

      Vol:
    E79-A No:8
      Page(s):
    1210-1216

    A single chip motion estimator is described dedicatedly for MPEG2 MP@HL moving pictures. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. A novel mechanism is introduced into the full-search procedure, which attempts the maximum possible reuse of reference pixels in order to reduce the bandwidth of the frame memory interface. The proposed motion estimator is integrated in a 0.6 µm triple-metal CMOS chip, which contains 1,450 K transistors on a 12.713.7 mm2 die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

  • Design of Ogg Vorbis Decoder System for Embedded Platform

    Atsushi KOSAKA  Hiroyuki OKUHATA  Takao ONOYE  Isao SHIRAKAWA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E88-A No:8
      Page(s):
    2124-2130

    This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.

  • Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect

    Yasuhiro OGASAHARA  Masanori HASHIMOTO  Takao ONOYE  

     
    PAPER

      Vol:
    E90-A No:4
      Page(s):
    724-731

    Capacitive and inductive crosstalk noises are expected to be more serious in advanced technologies. However, capacitive and inductive crosstalk noises in the future have not been concurrently and sufficiently discussed quantitatively, though capacitive crosstalk noise has been intensively studied solely as a primary factor of interconnect delay variation. This paper quantitatively predicts the impact of capacitive and inductive crosstalk in prospective processes, and reveals that interconnect scaling strategies strongly affect relative dominance between capacitive and inductive coupling. Our prediction also makes the point that the interconnect resistance significantly influences both inductive coupling noise and propagation delay. We then evaluate a tradeoff between wire cross-sectional area and worst-case propagation delay focusing on inductive coupling noise, and show that an appropriate selection of wire cross-section can reduce delay uncertainty at the small sacrifice of propagation delay.

61-65hit(65hit)